t0 labs

Foundational computing technologies

Advancing the state of the art

In ways nobody else thought possible

Research Areas

Application-specific Computing Computer Arithmetic Randomness

Clock and Time Synchronization

Contact us for research inquiries and technology transfer opportunities

Recent Projects

Quantum Randomness from FPGAs

Status

Commercialized at Arbitrand

Available to License

Years

2021-Current

Value Proposition

First TRNG in the cloud

scalable to terabits per second

Key Artifacts

TRNG IP for Xilinx Ultrascale+ and Alveo; AWS machine image

As of 2021, clouds still did not have a good solution for true random number generation for systems that needed it. Our solution was to use FPGA instances available in AWS and Azure to generate true random numbers, and software to distribute them over the network to systems that need them.

In doing so, we created a circuit that extracts shot noise from FPGA primitives. This makes random numbers that are exceptionally high-quality and immune to interference.

In a datacenter environment, our TRNGs can be put into servers that can produce and distribute 160 Gbps of true random data each. One rack of these servers scales to terabits per second in a 10 kW power footprint.

Synthesized TRNG on an FPGA

Division by Iterative Approximation for Small Microcontrollers

Division circuit

Microcontroller designers used to have to choose between division circuits that are small, but compute division results one bit at a time (restoring and non-restoring division), and division circuits that are fast, but large, using kilobyte-sized lookup tables and iterative refinement algorithms.

Our IP computes an initial approximation for an iterative division algorithm in a smaller circuit than a lookup table, which can be combined with a 32x32 multiplier to reduce its total area cost to <400 added logic gates.

As a result, our IP can be used to compute 32-bit integer divisions in <9 cycles, compared with 32 cycles for slow division methods. Including a control state machine with early termination, an integer divider based on our IP costs approximately 1000 equivalent gates compared to a system with no division. This also extends to float32 division in 5 cycles and float64 division in 8.

Status

Completed and Integrated

Published at ARITH 2023

Years

2022-2023

Value Proposition

3-4x faster division at a cost of <1000 logic gates

Key Artifacts

SystemVerilog code for integer/floating-point Mul/Div unit

Past Technology Transfers

ASICs for Bitcoin Mining

It was a simpler time. Bitcoins were worh several hundred dollars and mining was starting to become a serious business rather than a hobby. Some of us realized that SHA-2 is very easy to do on an ASIC, getting massive efficiency gains over previous state-of-the-art GPU miners.

Unlike competing ASICs arriving at the time, we used a full-custom SHA-2 implementation based on a fully-unrolled pipeline with extra stages added to reduce the critical path by 50% compared to a naive implementation, significantly improving hash rate per mm2 and per watt.

The ASIC was designed for synthesis in 40 nm technology with simple I/O interfaces and QFN packaging to amortize the cost of I/O interfaces over many gigahashes per second, and maximize the amount of silicon spent on hashing.

Customer

Private Buyer

Years

2012-2013

Value Proposition

Mine Bitcoins 1000x more efficiently than GPU

Delivered to Customer

Verilog code for ASIC

A Private Interdisciplinary Research Firm

Looking in "Green Strips"

Research is often referred to as "greenfield" or "brownfield." We think the best innovations lie in the thin green strips between brown fields: where market need is demonstrated, but other investigators aren't equipped to look.

Full-stack Research

For many projects, ranslation losses can creep in at the glue layers that show up between the lab and the field. We avoid these losses by starting projects with commercial intent, and working at all stages of the process to see them to fruition.

Ab Initio Innovation

We examine research projects from first principles, and try to understand underlying assumptions in the "normal" ways to solve problems, and whether they still hold.

Respect for Others

Our work is grounded in the idea that past researchers have done a good job in their fields, and we rely on that experience to learn about the current state of the art and find ways to improve it.

Principal Investigators

Photo of Nima Badizadegan

Nima Badizadegan

Nima Badizadegan is the founding investigator of T0 Labs. His research interests include computer systems, computer architecture, novel circuit techniques, applied math, and interdisciplinary research at the intersection of these fields. His past research projects have focused on ideas that require deep expertise in multiple disparate fields, stretching from analog circuits to distributed computing systems.

Badizadegan's past positions include serving as a Senior Software Engineer at Google, and an FPGA developer at Hudson River Trading. He is the inventor of over 10 US patents, and author of several scientific papers. Badizadegan also writes about practical software and hardware engineering on his technical blog.

Badizadegan holds degrees from Caltech and Boston University. He is a member of the ACM and the IEEE.